1. Field of the Invention
The present invention relates generally to pipelined analog-to-digital converter systems.
2. Description of the Related Art
Switched-capacitor pipelined signal converter systems arrange a plurality of converter stages so that they successively convert an analog input signal to corresponding digital bits. All but the last one of the stages provides a residue signal for processing by a succeeding one of the stages. The successive digital bits can then be temporally aligned so that they form a digital code which corresponds to the original input signal.
One class of these pipelined systems inserts a sampler ahead of the converter stages. The sampler forms samples of the input signal which are then presented to the initial stage for processing. Because the sampler consumes additional power and contributes to system noise and distortion, it is eliminated in a second class of pipelined converter systems. The sampler is often referred to as a sample-and-hold amplifier (SHA)) and, accordingly, the second class of systems is often said to have a “SHA-less” architecture.
Although SHA-less converter systems have the capability to reduce power consumption, noise and distortion, they introduce other problems because capacitors in the initial converter stage are now involved in a sampling process in addition to their conversion and residue generation processes. To resolve these problems, some SHA-less systems provide additional capacitors in the initial stage for the sampling process and/or insert additional buffering prior to the initial stage. These provisions, however, generally increase power consumption and noise and reduce speed capability. Other SHA-less systems provide a brief time for resetting of the stage capacitors but this additional time, of course, significantly reduces speed capability.